1. Field of the Invention
The invention relates to static MOS random access memories.
2. Brief Description of the Prior Art
Static MOS RAM's are commonly implemented utilizing six transistor storage cells. For example, see U.S. Pat. No. 3,594,736. The six-transistor storage cells are each comprised of cross-coupled back-to-back inverters. The outputs of each inverter are also connected, respectively, to two isolation MOSFETs. Each isolation MOSFET is coupled, respectively, to a separate sense-write conductor which has a substantial parasitic capacitance associated therewith. Each sense-write conductor is coupled to the source of a separate terminal MOSFET. Each termination MOSFET has its gate and source connected to a V.sub.DD conductor. Each of the storage cells is coupled between V.sub.DD and ground. In order to obtain low cost semiconductor RAMs, it is necessary that the storage cells be as small in size as possible. This requirement prevents the respective storage cells from being able to sink much sense current when they are selected during a read operation. At the beginning of a read operation, the two sense-write conductors coupled to the selected cell are normally at voltages equal to a MOSFET threshold voltage drop below V.sub.DD, and one of the sense-write conductors remains at V.sub.DD and the other is discharged to approximately zero volts by the selected storage cell. Typically, a column of storage cells is selected by means of two column select MOSFETS which couple the respective sense-write conductors to a pair of bit-sense conductors which have a large capacitance associated therewith. The selected storage cell must therefore discharge the total capacitance of the one sense-write conductor and one bit-sense conductor from almost V.sub.DD volts to nearly zero volts. Consequently, the access times of MOS static random access memories are relatively slow.